This invention relates to an apparatus for deriving clock pulses from return-to-zero data pulses.
In a return-to-zero digital pulse train, the presence of a pulse at a predetermined time represents a 1, while the absence of a pulse at that time represents a 0. Accordingly, it is generally necessary to have a train of clock pulses providing timing information in the identification of 1's and 0's among data pulses. In a communication system, it may be necessary to derive or "recover" clock pulses from the occurrences of the 1 pulses in the data.
One kind of circuit used to recover clock pulses from return-to-zero data is the phase-locked loop. In such a circuit, a voltage controlled oscillator generates clock pulses, which are then fed along with the data pulses to a phase detector. The phase detector generates a voltage which is some function of the difference in phase between a data pulse and a corresponding clock pulse. The voltage from the phase detector drives the voltage controlled oscillator to produce clock pulses which stay in phase with the data pulses.
The design of a phase-locked loop clock pulse recovery system becomes more difficult as the loop bandwidth, a measure of the speed of phase correction by the loop, increases. Another source of problems is the possibility of a long series of 0's or no data. In addition, because of the demanding requirements of phase-locked loops, it is important that the transfer function or gain of the phase detector be well behaved.